1. Field of the Invention
The present invention relates to a semiconductor device including at least one of memory unit and a semiconductor module including at least memory units, and more particularly relates to a semiconductor device has at least one of memory unit which can lay over one after another and a semiconductor module has at least a plurality of memory units which can lay over one after another. Further, the invention relates to a semiconductor device has at least one of memory unit which can lay over to at least one of another memory unit of the same structure and a semiconductor module has at least a plurality of memory units which can lay over to each other and formed the same structure.
2. Description of the Related Art
Semiconductor devices are strongly required to be compact as lap top personal computers (PC), portable terminal equipment (PDA), portable phones or the like have become popular. Especially, semiconductor memories for storing a large amount of information such as a dynamic random access memory (called xe2x80x9cDRAMxe2x80x9d hereinafter) are being required to have an increased storage capacity.
In the foregoing DRAM, a storage capacity realized by a single semiconductor chip depends upon minute machining precision in a semiconductor manufacturing process. In order to assure a sufficient storage capacity, portable equipment should be provided with a plurality of DRAMs (i.e. a plurality of semiconductor chips). Usually, the plurality of DRAMs are two-dimensionally mounted on the same plane of a printed circuit board such as a mother board, daughter board or the like of the portable equipment.
However, with the foregoing mounting structure, the DRAMs occupy a large space on the printed circuit board, so that it has been very difficult to downsize the portable equipment. In order to overcome such a problem, it has been proposed to three-dimensionally mount DRAMs on a printed circuit board.
Referring to FIG. 16 of the accompanying drawings, a synchronous DRAM system (called xe2x80x9cSDRAMxe2x80x9d system hereinafter) 100 comprises: four memory banks 101 to 104; a clock buffer circuit 110; a command decoding circuit 111; a control signal generating circuit 112; an address buffer circuit 113; a mode register circuit 114; a refresh counter circuit 115; a column counter circuit 116; a data controlling circuit 117; and a data output buffer circuit 118. Each of the memory banks 101 to 104 houses a memory cell array 130, a column decoding circuit 131, a row decoding circuit 132, and a sense amplifier 133 thereon.
A storage capacity of each of the memory banks 101 to 104 is 16-Mbits, so that the SDRAM system 100 has a total storage capacity of 64-Mbits. The memory cell array 130 receives 12-bit row address signals and 8-bit column address signals. There are provided 16 data lines. These values depend upon the storage capacity of the SDRAM system 100. For instance, an SDRAM system having a storage capacity of 256-Mbits uses 13-bit row address signals and 9-bit column address signals.
The clock buffer circuit 110 receives clock signals CLK and CKE. The command decoding circuit 111 receives not only the clock signal CKE but also a chip selecting signal CS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and an address signal A10. The address buffer circuit 113 receives address signals A10, A0-A9 and A11, and bank selecting signals BS0 and BS1. Further, the data output buffer circuit 118 sends and receives data signals DQ0 to DQn.
The SDRAM system 100 writes and reads data according to the operation flowchart shown in FIG. 17.
(1) Bank Active Operation
First of all, the address signals A0 to A11 are inputted to the address buffer circuit 113. The 12-bit row address signals are determined on the basis of the address signals A0 to A11 (in step 120). The row address strobe signal RAS, column address strobe signal CAS, and write enable signal WE are inputted to the command decoding circuit 111. When the row address strobe signal has a low level xe2x80x9cLxe2x80x9d, the column address strobe signal CAS has the high level xe2x80x9cHxe2x80x9d, and the write enable signal WE has a high level xe2x80x9cHxe2x80x9d (in step 121), the chip selecting signal CS is then inputted to the command decoding circuit 111. If the chip selecting signal CS has the low level xe2x80x9cLxe2x80x9d (in step 122), the SDRAM system 100 will be selected. In this state, the bank selecting signals BS0 and BS1 are inputted to the address buffer circuit 113 (in step 123). One of the memory banks 101 to 104 is activated in response to the bank selecting signals BS0 and BS1. For instance, it is assumed that the memory bank 101 is activated. Even if the chip selecting signal CS has the high level xe2x80x9cHxe2x80x9d in this state, no data is written and read since the SDRAM system 100 has not been activated. The row address signal CAS is input to the activated memory bank 101.
(2) Data Write Operation and Data Read Operation
The activated memory bank 101 receives the 9-bit column address signals CAS in response to the address signals A0 to A8 inputted to the address buffer circuit 113 (in step 124). The command decoding circuit 111 receives the row address strobe signal RAS, column address strobe signal CAS and write enable signal WE. In this state, if the row address signal RAS has the high level xe2x80x9cHxe2x80x9d, the column address strobe signal CAS has the low level xe2x80x9cLxe2x80x9d, and the write enable signal WE has the high level xe2x80x9cHxe2x80x9d (in steps 125 and 126), in the memory cell array 130 of the activated memory bank 101, a data stored at a memory cell of an address, which is selected on the basis of the row address signal RAS and the column address signal CAS, is read from the memory cell (in step 127). The data is outputted as the data signal DQ from the data output buffer circuit 118. On the other hand, if the write enable signal WE has the low level xe2x80x9cLxe2x80x9d, in the memory cell array 130 of the activated memory bank 101, the data is written into the memory cell of the address, which is selected on the basis of the row address signal RAS and the column address signal CAS (in step 128). The data written into the memory cell is inputted to the data output buffer circuit 118 as the data signal DQ.
The SDRAM system 100 to and from which the data is written and read is activated in response to the chip selecting signals CS.
When the SDRAM system 100 shown in FIG. 16 is packaged as one semiconductor memory and a plurality of SDRAM systems 100 are simply stacked on a printed circuit board, a terminal for supplying the chip selecting signal (i.e. a chip selecting lead pin) is commonly used for all of the SDRAM systems 100. An external device can neither activate a particular SDRAM system 100 nor write the data into it or read the data therefrom.
Japanese Patent Laid-open Publications No. Hei 2-290048 and No. Hei 6-342874 disclose the inventions which can overcome the foregoing technical problems.
In Japanese Patent Laid-open Publication No. Hei 2-290048 (called xe2x80x9cReference 1xe2x80x9d), packages 131 to 134 of the tape-automated bonding type (called xe2x80x9cTABxe2x80x9d) are stacked on the printed circuit board 130 as shown in FIG. 18. The packages 131 to 134 are respectively provided with outer leads 135A to 135D for sending common signals such as an address signal, a power source and so on, and outer leads 136A to 136D for sending the chip selecting signal CS to the packages 131 to 134. The outer leads 136A to 136D are branched into a plurality of sections, which are dislocated one by one and are electrically connected to terminals 130A to 130D of the printed circuit board 130 via the outer leads 137A to 137D. In other words, the chip selecting signal CS can be independently supplied to the packages 131 to 134 via the outer leads 137A to 137D.
In the Japanese Patent Laid-open Publication No. Hei 6-342874 (called xe2x80x9cReference 2), the package substrates 141 to 144 are stacked on the printed circuit board 140 as shown in FIG. 19. The package substrates 141 to 144 are respectively provided with the front electrodes 145A to 145H and the rear electrodes 146A to 146H, which are electrically connected via the through-holes. Further, the front electrodes 145A to 145H and rear electrodes 146A to 146H are arranged in a staggered manner, so that the package substrates 141 to 144 can independently receive the chip selecting signal.
However, the foregoing inventions of the References 1 and the References 2 seem to suffer from the following problems.
(1) In the Reference 1, the outer leads 137A to 137D are respectively connected to one end each of the branched outer leads 136A to 136D, so that the chip selecting signal CS can be independently supplied to the packages 131 to 134. Therefore, it is possible to increase the storage capacity by stacking a plurality of the packages 131 to 134 having the same structure. When the four packages 131 to 134 are stacked, the four outer leads 137A to 137D should be provided. Each of the outer leads 136A to 136D is branched into four sections. Further, if eight packages are stacked, eight outer leads are required. Each of the outer leads should be branched into eight sections. In other words, the packages 131 to 134 are enlarged depending upon the number of branched sections of each of the outer leads 136A to 136D.
(2) With the Reference 2, the front electrodes 145A to 145H and rear electrodes 146A to 146H are arranged in the staggered manner in order to supply the chip selecting signals CS. Thus, the chip selecting signals CS are separately supplied to the package substrates 141 to 144. It is possible to increase the storage capacity by stacking the package substrates 141 to 144 having the same structure. As with the Reference 1, the number of rows of the front electrodes 145A to 145H and rear electrodes 146A to 146H increases in accordance with the increase of the chip selecting signals, which would inevitably enlarge the package substrates 141 to 144.
(3) In the References 1 and 2, the more the packages 131 to 134 or the package substrates 141 to 144, the more chip selecting signals CS, and the more terminals for supplying the chip selecting signals CS. The packages 131 to 134 or the package substrates 141 to 144 have to be enlarged depending upon the increase in the number of the foregoing terminals. Therefore, it has been very difficult to increase the storage capacity of three-dimensionally stacked devices.
According to the present invention, a semiconductor device comprises: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit which includes at least a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned to the memory unit and the memory unit selecting signal, and an identifier generating circuit for generating identifiers for other memory units on the basis of the identifier.
According to embodiment of the present invention, the identifier generating circuit of the semiconductor device is mainly constituted by an adder circuit or a subtracter circuit.
According to embodiment of the present invention, in the semiconductor device, the identifier is one bit data or a plurality of bit data, and the identifier generating circuit is an adder circuit for carrying the identifier data of the memory unit bit by bit.
According to embodiment of the present invention, the identifier generating circuit of the semiconductor device is the adder circuit for carrying the identifier of the memory unit by a half bit.
According to embodiment of the present invention, the identifier generating circuit of the semiconductor device is electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply, and the standard voltage power supply voltage or the circuit operation power supply is used as the identifier.
According to embodiment of the present invention, the memory unit selecting circuit of the semiconductor device is a comparator for compares the identifier with the memory unit selecting signal.
According to embodiment of the present invention, the memory unit of the semiconductor device is either a DRAM (including SDRAM or the like) or a static random access memory (SRAM) or a non-volatile memory which is a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or an electrically erasable programmable read-only memory (EEPROM).
According to embodiment of the present invention, in the semiconductor device, the selecting signal terminal which receives the memory unit selecting signal is a surplus signal terminal out of address signal terminals which are used for selecting address of the memory unit.
According to the present invention, a semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit which is provided outside the memory unit and includes at least a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and a memory unit selecting signal, and an identifier generating circuit for generating identifiers for other memory units on the basis of the identifier of the memory unit.
According to embodiment of the present invention, in the semiconductor device, the memory unit and the identifying unit are constituted by separate semiconductor chips.
According to embodiment of the present invention, in the semiconductor device, the semiconductor chips constituting the memory unit and the identifying unit are constituted by separate packages.
According to embodiment of the present invention, in the semiconductor device, the semiconductor chips constituting the memory unit and the identifying unit are constituted by the same package.
According to embodiment of the present invention, the selecting signal terminal of the semiconductor device is provided in the semiconductor chip constituting the identifying unit.
According to the present invention, a semiconductor module comprising: a first memory unit; a second memory unit positioned on or by the first memory unit; a first selecting signal terminal provided in the first memory unit and for receiving a memory unit selecting signal which is common to a plurality of memory units; a second selecting signal terminal provided in the second memory unit and for receiving the memory unit selecting signal which is common to a plurality of memory units; a first identifying unit including at least: a first memory unit selecting circuit for selecting the first memory unit on the basis of a first identifier assigned thereto and the memory unit selection signal; and a first identifier generating circuit for generating a second identifier for the second memory unit on the basis of the first identifier; and a second identifying unit including at least: a second memory unit selecting circuit for selecting the second memory unit on the basis of the second identifier assigned thereto and the memory unit selection signal; and a second identifier generating circuit for generating a third identifier for a third memory unit on the basis of the second identifier.
According to embodiment of the present invention, the first identifier generating circuit and the second identifier generating circuit of the semiconductor module are mainly constituted by an adder circuit or a subtracter circuit.
According to embodiment of the present invention, the first identifier generating circuit of the semiconductor module is electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply, and the standard voltage power supply or the circuit operation power supply is used as the first identifier.
According to embodiment of the present invention, in the semiconductor module, the first memory unit selecting circuit is a comparator for compares the first identifier and the memory unit selecting signal, and the second memory unit selecting circuit is a comparator for compares the second identifier and the memory unit selecting signal.
According to embodiment of the present invention, in the semiconductor module, the second memory unit is stacked on the first memory unit.
According to embodiment of the present invention, in the semiconductor module, the second memory unit is juxtaposed to the first memory unit.
According to embodiment of the present invention, semiconductor module further comprising at least one memory unit and at least one identifying unit.
According to the present invention, a semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit at least including an identifier generating circuit provided with at least a fuse element for generating an identifier assigned to the memory unit, and a memory unit selecting circuit for selecting the memory unit on the basis of an identifier assigned thereto and the memory unit selecting signal.
According to embodiment of the present invention, in the semiconductor device, the identifier generating circuit further includes a resistance element; the fuse element has one end thereof electrically connected to a standard voltage power supply for a circuit system and the other end thereof electrically connected to the memory unit selecting circuit and one end of the resistance element; and the resistance element has the other end thereof electrically connected to the circuit operation power supply for the circuit system.
According to embodiment of the present invention, the resistor element of the semiconductor device has a resistance value which is higher than a resistance value of the fuse element.
According to the present invention, a semiconductor device comprising: a memory unit; a selecting signal terminal for receiving a memory unit selecting signal which is common to a plurality of memory units; and an identifying unit at least including an identifier generating circuit provided with at least a wire for generating an identifier for the memory unit, and a memory unit selecting circuit for selecting the memory unit on the basis of the identifier assigned thereto and the memory unit selecting signal.
Further, according to embodiment of the present invention, the wire of the semiconductor device has one end thereof electrically connected to a standard voltage power supply for a circuit system or a circuit operation power supply for a circuit system and the other end thereof electrically connected to the memory unit selecting circuit.